Generally, wiring technology refers to a technology for realizing interconnections, power supplying routes, and signal transmission routes of transistors in an integrated circuit (IC).
Recently, as design rules have been reduced due to the higher integration of semiconductor devices, memory cells have been stacked. Therefore, interconnection lines are formed in a multi-layer structure in order to freely perform wiring design and easily set resistance and current capacities of interconnection lines.
In addition, as the aspect ratio of a contact hole or via hole has increased due to the reduction of design rules, multi-layer interconnection lines have been electrically connected with one another using a contact plug.
Additionally, a contact area has become larger because a contact hole or via hole has been formed at nearly the same width as a lower wire in order to ensure a contact resistance corresponding to higher integration.
Hereinafter, a conventional method of forming an interconnection line will be described in detail with reference to FIG. 1A to FIG. 1C.
Referring to FIG. 1A, a lower interlayer insulating layer 20 is formed on a semiconductor substrate 10, and a metal layer 30 used for a wiring material is deposited on the lower interlayer insulating layer 20. Subsequently, a first photoresist pattern 40 is formed on the upper part of the metal layer 30 by performing a photolithography process.
Referring to FIG. 1B, a lower wire 31 is formed by etching the metal layer 30 using the first photoresist pattern 40 (referring to FIG. 1A) as a mask, and the first photoresist pattern 40 is removed by a well-known method. Subsequently, an upper interlayer insulating layer 50 is formed on the lower interlayer insulating layer 20 in order to cover the lower wire 31, and a second photoresist pattern (not shown) is formed on the upper interlayer insulating layer 50 by performing a photolithography process.
Thereafter, a via hole 60 is formed by performing a plasma etching process using the second photoresist pattern as a mask, and the second photoresist pattern is removed by a well-known method. When the via hole 60 having nearly the same width as the lower wire 31 is formed, the lower wire 31 is exposed.
Referring to FIG. 1C, a tungsten layer used for a plug material is deposited on the entire surface of the substrate 10 in order to fill the via hole 60, and a tungsten contact plug 70 contacted with the lower wire 31 is formed by removing the tungsten layer through a chemical mechanical polishing (CMP) process to the degree that the upper interlayer insulating layer 50 can be exposed.
Subsequently, an upper wire 80 that is electrically connected to the lower wire 31 through the contact plug 70 is formed by depositing a metal layer used for a wiring material on the entire surface of the substrate 10, and by pattering the metal layer through a photolithography process and an etching process.
However, even if a contact is formed as mentioned above by forming the via hole 60 having nearly the same width with the lower wire 31, there is a limitation to increasing a contact area due to the higher integration of semiconductor devices.
In addition, the lower wire 31 may be severely damaged in the process of etching the upper interlayer insulating layer 50 because a substantial amount of polymer gases and physical etching factors, such as a high RF (Radio Frequency) power and a low pressure, are required to form the via hole 60 having the high aspect ratio by a plasma etching process.
Accordingly, characteristics and reliabilities of semiconductor devices are deteriorated because an excellent contact resistance characteristic corresponding to the higher integration can rarely be ensured.